Roles & Responsibilities

Responsibilities:

Provide Service Management to supervise the network system and continuously monitor alerts ...

Position Summary

• To manage the company trouble-ticketing systems, provide incident reporting, service performance reporting and recording of spares inventory.

Job Responsibilities ...

Roles & Responsibilities

Job Description:

Responsible for the monitoring of servers, systems & networks in an environment requiring 24 X 7 X 365 uptime. ...

Job Description:

Responsible for the monitoring of servers, systems & networks in an environment requiring 24 X 7 X 365 uptime.

Provides escalation point for all system-generated events/alerts and user-generated incidents. ...

Roles & Responsibilities

Responsibilities:

Provide Service Management to supervise the network system and continuously monitor alerts ...

Job description

Network Operations Centre (NOC) Engineer is responsible to conducts, performs, delegates, and monitoring local and oversea smart hands and remote hands services for IT companies datacenter equipments. NOC Engineer is also responsible to monitor overseas Field Engineers/Network Engineers scope of work, work schedule, datacenter access clearance, materials and equipments used in smart hands and remote hands support. NOC Engineer is to manage IT operations on support request, issue ticket, operation documentation, escalation and subsequent related operations in providing support based on ServiceLevel Agreement (SLA) in 24 hours and 7 days a week. NOC Engineer is required to carefully track and document all related work in details according to standard operations procedure.

NOC Engineer must be able to:- ...

* 12 hrs rotating shifts, 4334 (4 days work 3 days off / 3 days work 4 days off)

* Location: Serangoon North

* Basic + Shift Allowance + OT pay ...

Provide outstanding customer service to users over phone, email, and/or live chat regarding product selection, services and issues.

Focus on delivering on key results like customer satisfaction, first time resolution, efficiency and quality metrics.

Proactively develop innovative ideas to drive process, product and support improvements.

Provide outstanding customer service to users over phone, email, and/or live chat regarding product selection, services and issues.

Focus on delivering on key results like customer satisfaction, first time resolution, efficiency and quality metrics.

Proactively develop innovative ideas to drive process, product and support improvements.

* 12 hrs rotating shifts, 4334 (4 days work 3 days off / 3 days work 4 days off)

* Location: Serangoon North

* Basic + Shift Allowance + OT pay ...

Roles & Responsibilities

To apply, It will be great if you could share your CV to

hoonteck.tan@randstad.com.sg ...

Great opportunity to work for a multi billion tech giant

Exposure to latest technology in a data center environment

About the company ...

Great opportunity to work for a multi billion tech giant

Exposure to latest technology in a data center environment

About the company ...

Position: Security Operations Command Engineer (SOC) - IT & OT

Location: Jurong East or Loyang (TBC)

Terms: Full-time ...

Roles & Responsibilities

Salary: $2400-$2800+allowances+OT=>$3300

Industry: Engineering ...

Job Description: - Designs, develops, and builds digital circuits for custom blocks including SRAM, register files, memory compilers, and caches. - Designs floorplans, performs circuit design, schematic entry, simulation for major blocks, and verifies functionality to optimize custom circuit for power, performance, area, timing, and yield goals. - Creates block level DFT models, develops memory test tools, and improves and automates flows and methodologies to ensure streamlining of design. - Collaborates cross functionally to report design progress and to collect, track, and resolve any performance and memory circuit design issues. - Optimizes performance, power, and area, reduce leakage of circuits, and drive characterization of individual memory instances and memory compilers. - Works with architecture and layout teams to design circuit for best functionality, robustness, and electrical capabilities. Qualifications: Candidate should possess a BSEE or equivalent with 6+ years/MSEE or equivalent with 8+ years design experience in the structural/physical design domain. Additional qualifications include: - Technical lead Role in delivery of multiple SoCs, ASICs, or Sub Chips- Proficient in all aspects of physical design from RTL - GDSII (Synthesis, Floorplan, Auto Place and Route, Clock Tree Synthesis). - Expert level knowledge on Synopsys based implementation tools - ICC2, Fusion Compiler - Experienced in CTS methodologies - CTS, MPCTS, CTMESH - Expertise in High frequency timing closure at sub chip or at SoC - Experienced in Full chip Layout Verification - DRC and LVS - Experience on 7nm and lower a plus - Possesses strong Technical Aptitude, Self-Driven, Analytical, Ability to work in diverse teams and Ability to multi-task. - Motivated and Passionate to learn improvements in tool flows and methodologies - Good Communication Skills - Partner with multiple stake holders to deliver the key responsibilities - Hands-on experience with scripting languages such as Python, Perl, TCL

Roles & Responsibilities

* 12 hrs rotating shifts, 4334 (4 days work 3 days off / 3 days work 4 days off), 7am - 7pm , 7pm - 7am

* Location: Serangoon ...

Join Our Team at Thatz International Pte Ltd

Ready to embrace the latest opportunities in the ever-changing tech world? At

Thatz International Pte Ltd ...

Job Responsibilities • Hardware architecture end-to-end lifecycle ownership. • Drive Architecture/Software/Hardware co-design and collaboration on features set. • Perform feasibility analysis including SoC area, performance and power estimates. • Guide an efficient system/hardware/software architecture to meet product requirements. • Assess and guide system integration feasibility, feature and implementation trade-offs of new technologies. • Review, challenge and influence roadmaps, and set technology intercept targets for future SoCs. • Recognize and understand technology trends. • Specification ownership/authoring for the High-level architecture spec or key SoC features. • Hardware specification authoring, review, and System C model development (where applicable). • Review downstream specifications and verification plans in ASIC, software and/or platform to ensure requirements are followed. • Architectural validation plan and execution. • Post-Silicon production support with silicon debug and publishing of customer documentation. • Industry standards tracking & 3rd party IP technical evaluation. • Patenting novel parts of system architecture. Qualifications • Possess a Bachelor's, a Master's degree or a Ph.D. in Electronics Engineering, Computer Engineering, or equivalent • Have meaningful industry expertise in SoC architecture definition - Clocks, Resets, Automotive safety, Interconnects, Memory Controller, Boot, Virtualization, Power Management, Security, System Performance, IO technologies, (PCIE, Camera Interfaces, etc), Multimedia accelerator pipelines, CPU/GPU coherency, Platform integration. • Must have outstanding SoC and system architecture fundamentals backed with substantial experience. This means a good understanding of power and performance tradeoffs, transient and steady-state performance states, idle and dynamic power states, as well as how SoC data and control flows interact. • Sound understanding of Microprocessor Subsystems, Memory Controllers and Communication Fabrics. • Good understanding the Digital ASIC Flow and Debug methodology. • Solid understanding of electrical and thermal considerations at the chip, package and system levels. • Good understanding of hardware-software interfaces. • Demonstrate and comfortable communicating and solving issues at all levels of architecture definition from micro-architecture to system level to software architecture. • Excellent communication skills across organizations and at the executive level. Excellent written skills for clear and concise reporting. • Excellent organization skills to prioritize conflicting requirements, and strong cross-site teamwork skills with the willingness to work independently. • Application of Machine Learning/ Artificial Intelligence in SOC design and flows across all functions • SOC design and bridge the gap between verification, emulation and bring up/validation • Shift left methodology HW/SW/FW co-verification/emulation Methodology

Locations: Various locations across Singapore (depending on deployment)

Working hour: 9am – 630pm, Monday to Friday(depending on the site operation hour

No experience is required. Training is provided ...

Job Description: You will be part of the global ITVG (IP Testchip and Validation Group) group that is responsible to develop SOC Testchip for Hard IPs and Soft IPs on leading edge process nodes that powers Intel products across Client, Data Center, Networking, Graphics, AI and enabling Intel Foundry Customers. You will also be part of the cohesive and diverse team that is responsible to develop E2E Bootable SOC Testchip where you can directly apply your industry ASIC knowledge - ARM, AMBA protocols - CHI/AXI/AHB/APB, PCIE, DDR, UCIE on both SOC and subsystem verifications. - In this role, you will collaborate with SOC architects and design engineers to verify the design and performance of SoC projects, ensuring bug-free first silicon - As a key team member, you will also contribute to our verification methodology and own Verification Strategy for Block/Sub-system and SoC Test plans. - Develop and execute verification plans based on design specifications and collaboration with architects and designers - Utilize constrained random verification, functional coverage, system Verilog assertions, code coverage and assertions to achieve goals - Track and debug failures and work with designers to resolve them - Assist with bring-up and debug of SoC Projects. Qualifications: Candidate must have a Bachelor, Master or PhD Degree in Computer Engineering, Electrical Engineering, Computer Science, Microelectronics, VLSI or a related field with >8 years of ASIC pre-silicon design/verification. Candidate must possess strong fundamentals in the following areas. - Good understanding of SV, OVM, UVM and verification methodologies - Experience in using verification tools such as VCS, DVE, Verdi etc - AMBA Protocols - CHI/AXI/AHB/APB - Scripting in Python, Perl, TCL Have strong fundamental knowledge in DDR, PCIE, ARM AMBA Protocols, DMA, I2C, SPI Working knowledge with X86/ARM cores. Experience in Formal Verification is an added advantage. Strong in problem-solving and debugging various simulation failures independently. Strong written and oral communication skills able to communicate well with counterparts and key stakeholders including cross-site partners.

We are hiring this position for a fast-growing company in semiconductor manufacturing industry.

Responsibility

1. Responsible for design works including but not limited to: PCIe/CXL design integration work, and PCIe related developing work; or ethernet/RoCE related developing work; or D2D/UCIe design integration work. ...

We are hiring this position for a fast-growing company in semiconductor manufacturing industry.

Responsibility

1. Responsible for design works including but not limited to: PCIe/CXL design integration work, and PCIe related developing work; or ethernet/RoCE related developing work; or D2D/UCIe design integration work. ...

Roles & Responsibilities

Position: Security Operations Command Engineer (SOC) - IT & OT

Location: Jurong East or Loyang (TBC) ...

Roles & Responsibilities

Responsibilities

Attend to escalations from internal and external stakeholders ...

Provide outstanding customer service to users over phone, email, and/or live chat regarding product selection, services and issues.

Focus on delivering on key results like customer satisfaction, first time resolution, efficiency and quality metrics.

Proactively develop innovative ideas to drive process, product and support improvements.

Select how often (in days) to receive an alert:

Provide engineering supporting an SOC environment.

Plan, test and deploy patches for SOC systems. ...

Responsibilities:

Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.

Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance. ...

Roles & Responsibilities

Responsibilities:

Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design. ...

Select how often (in days) to receive an alert: Provide engineering supporting an SOC environment. Plan, test and deploy patches for SOC systems.

Work with Dev Ops and SOC team to plan for developmental work. Manage lifecycle of security log sources, including onboarding, modifying, and decommissioning of log sources. Perform data engineering to extract, transform, load for security monitoring.

Work with SOC team to deploy new features and changes to the SOC environment. Maintain up-to-date technical documentation for SOC environment. Stand-by support after office hours for support issues. ...